Deep trench etching (DSIE) technology has been widely used in manufacturing of semiconductors, such as Micro-Electro-Mechanical Systems (MEMS) and power MOSFET (Power MOS). In a conventional deep trench etching process, photoresist is used as a masking layer, which is then patterned according to designed pattern layout using a photolithography process. After that, a part to be etched is exposed by the etching pattern on the patterned photoresist. During the deep trench etching process, an etching deepness is usually greater than 300 μm, while the etching critical dimension (CD), i.e., the width of the etched trench or the diameter of the etched hole, is usually greater than 500 μm. Due to the long time and high deepness of deep trench etching process, the masking layer may be damaged and morphology changes to which may occur due to ion etching during the etching process, such that the critical dimension for the etching gradually increases along with the time. In addition, during the deep trench etching process, the damage levels to the masking layer at a center position and at an edge position of the wafer are different using the conventional etching equipment, which further increases the difference between the etching structures at the center position and at an edge position of the wafer. Generally speaking, a critical dimension of an etching structure at the edge of the wafer is greater than that at the center of the wafer, and this etching critical dimension difference for different positions may cause adverse effects to the product performance.